Synchronous sequential systems rely on globally synchronized clocks. With the increase in clock rates, low-skew clock distributions are becoming increasingly critical to achieving design speed objectives. High-speed circuits may also require clocks with programmable duty cycle and delay. For all these applications, comprehensive clock management is necessarily implemented on a chip. The Phase- and Delay-Locked Loops are used to achieve low clock skew distributions. The principles of frequency synthesis, by which the clock rates can be multiplied and divided, are outlined, together with its applications. The basic idea of the active closed-loop clock skew compensation is to reduce exactly as much clock skew as needed. This is achieved by using circuitry that can generate a clock signal, or modulate its delay. Typically, such compensation is placed in incoming clock buffers. The overall effect is equivalent to that of inserting negative delay in the clock path. Note that any of the passive techniques for reducing clock skew with layout and clock network speed optimizations cannot completely reduce the clock skew. Only the use of the closed-loop clock skew reduction can lead to that goal. Active skew compensation can be achieved by using either PLLs or DLLs—both compare the input and feedback clocks, and guarantee that they are aligned. The difference between the two is in the use of the internal delay line. In DLLs, the delay line inserts the controlled delay between the input and output clock. In PLLs, the delay line is used as a ring oscillator that is realized by closing the loop and guaranteeing that the inverted output of the delay line is fed back. Hence, while DLLs only delay the incoming clock signals, the PLLs actually generate a new clock signal in such a way that the delay in the clock distribution is completely eliminated.
The basic delay locked loop (DLL) circuit consists of a phase detector, a loop filter and a voltage controlled delay line. The phase detector measures the relationship (lead/lag) between the input and the output signals. The loop filter integrates the phase error and cancels high frequency jitter. Then the output of loop filter changes the voltage of the voltage controlled delay line to make the input signal and the output signal in phase.
Operation of the DLL is as follows. First, the phase detector detects the output signal leading/lagging the input signal. The difference in phase between the input and the output is called phase error. Then, phase error is integrated in the loop filter. Depending on the output voltage of the loop filter, it either makes voltage controlled delay with larger or smaller delay, until the phase error is zero or very small. At this point, it is called “locked”. When the DLL is locked, the delay time between the input and the output signals is equal to the static phase offset.
But in a video system, a higher resolution display requires a higher frequency pixel clock, and smaller DLL jitter. The basic DLL circuit as above can not meet the requirements.